huf 76633p3_f085 38a, 100v , 0.036 oh m, n-channel, logic level ultrafet? power mosfet packaging symbol features ? ultra low on-resistance -r ds (on ) = 0 .035 ?, v gs = 10 v -r ds (on ) = 0 .036 ?, v gs = 5v sim ulation models - temperature compensated pspice? and saber? electrical models - spice and saber thermal impedance models - www.fairchildsemi.com peak current vs pulse width curve uis rating curve switching time vs r gs cu rve s or dering informat ion ab solut e maximum ratings t c = 25 o c, unles s otherwise specified product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html for severe environm ents, see our automotive hufa series. all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certif ication. jedec to-220ab drain ( flange) drain sou rce gate d g s p art number package brand huf76633p3 _f085 t ratings units drain t o s ource voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . v dss 100 v drain t o ga te voltage (r gs = 20k ? ) (no te 1) . . . . . . . . . . . . . v dg r 100 v g ate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16 v drain cur rent conti nuous (t c = 25 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . i d cont inuous (t c = 25 o c, v gs = 10 v) (figure 2) . . . . . . . . . . . . . i d cont inuous (t c = 100 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . i d cont inuous (t c = 100 o c, v gs = 4.5v ) (figure 2) . . . . . . . . . . . i d pul sed drai n current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 38 39 27 27 f igure 4 a a a a pu lsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uis figures 6, 17, 18 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derat e abov e 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 0.97 w w/ o c o perating and st orage temperature . . . . . . . . . . . . . . . . . t j , t st g - 55 to 175 o c m aximum te mperature for soldering leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . t l p ack age body for 10s, see techbrief tb334 . . . . . . . . . . . . . t pk g 300 260 o c o c no tes : 1. t j = 25 o c t o 150 o c. ca ution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress only ratin g and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. d ata sheet april 2012 o -220ab 76633p qualified to aec q101 rohs compliant ?2012 f airchild semiconductor corporation huf76633p3_f085 rev. c 1 www.fairchildsemi.com 1
elect rical specifications t c = 2 5 o c, u nless otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (f igure 1 2) 100 - - v i d = 250 a, v gs = 0v , t c = - 4 0 o c (f igure 12) 90 - - v zero gate voltage drain current i dss v ds = 95v, v gs = 0v - - 1 a v ds = 90v, v gs = 0v , t c = 150 o c - - 250 a g ate to source leakage current i gss v gs = 16v - - 100 na on state specifications gate to source threshold voltage v gs(t h ) v gs = v ds , i d = 250 a (f igure 11) 1 - 3 v drain to source on resistance r ds(o n ) i d = 39a, v gs = 10 v ( figures 9, 10) - 0.029 0.035 ? i d = 27a, v gs = 5v (figure 9) - 0.030 0.036 ? i d = 27a, v gs = 4. 5v (f igure 9) - 0.031 0.037 ? thermal specifications thermal resistance junction to case r jc to -220 and t o-263 - - 1.03 o c/w th ermal resis tance junction to ambient r ja --6 2 o c/w sw it ching specifications (v gs = 4.5v) turn-on time t on v dd = 50v , i d = 27a v gs = 4.5 v , r gs = 4. 7 ? (f igures 15, 21, 22) - - 185 ns turn-on delay time t d(o n ) -12- n s rise time t r - 110 - ns turn-off delay time t d( off) -43- n s fall time t f -58- n s turn-off time t off - - 150 ns switching specifications (v gs = 10v) t u rn-on time t on v dd = 50v , i d = 39a v gs = 10v, r gs = 5. 1 ? (f igures 16, 21, 22) - - 95 ns turn-on delay time t d(o n ) -7. 5 - ns rise time t r -55- n s turn-off delay time t d( off) -63- n s fall time t f - 83 - ns t urn-off time t off - - 220 ns gate charge specifications total gate charge q g( tot) v gs = 0v to 10v v dd = 50v, i d = 27a, i g(r e f) = 1. 0ma (f igures 14, 19, 20) -5667nc gate charge at 5v q g( 5) v gs = 0v to 5v - 30 37 nc threshold gate charge q g(t h ) v gs = 0v to 1v - 2 2.4 nc gate to source gate charge q gs -6 -nc gate to drain ?miller? charge q gd -15- n c capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v , f = 1 mhz (figure 13) - 1820 - pf output capacitance c oss - 415 - pf reverse transfer capacitance c rs s - 115 - pf s our c e to drain diode specifications pa rame ter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 27a - - 1.25 v i sd = 13a - - 1.0 v reverse recovery time t rr i sd = 27a , di sd /d t = 100a/ s - - 113 ns reverse recovered charge q rr i sd = 27a , di sd /d t = 100a/ s - - 425 nc h uf76633p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 2
t ypical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum cont inuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capab ility t c , case t emperature ( o c) p ow er dissipation multiplier 0 0 25 50 75 100 17 5 0. 2 0.4 0. 6 0.8 1.0 1.2 125 15 0 10 20 30 40 50 0 25 50 75 100 125 150 17 5 i d , drain current ( a) t c , cas e temperature ( o c) v gs = 1 0v v gs = 4 .5 v 0. 1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.0 1 2 t, rectangular pulse duration (s) z jc , normal ized si ngle pu lse no tes: dut y factor: d = t 1 /t 2 pea k t j = p dm x z jc x r jc + t c p dm t 1 t 2 dut y cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 t herm al impedance 10 0 500 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 30 i dm , p eak current (a) t , pul se width (s) t ransconductance m ay limit current in this region t c = 2 5 o c i = i 25 17 5 - t c 15 0 f or temperatures above 25 o c d er ate peak current as fo llows: v gs = 5 v v gs = 10v h uf7 6633p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 3
f igure 5. forward bias safe operating area note: refer to fairchild application notes an9321 and an 9322. figure 6. unclamped inductive switching capability figure 7. transfer characteristics fig ure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature t ypical performance curves ( continued) 10 100 11 01 0 0 200 1 30 0 10 0 s 10 ms 1m s v ds , drain to source voltage (v) i d , drai n current (a) li mi ted by r ds (o n) area m ay be op eration in this t j = m ax rated single pulse t c = 2 5 o c 0.0 01 0.01 0.1 1 1 0 10 100 1 500 i as , av alanche current (a) t av , t im e in avalanche (ms) t av = (l)( i as ) /( 1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/ r)ln[(i as * r)/ (1.3*rated bv dss - v dd ) + 1] st arting t j = 2 5 o c st art ing t j = 1 50 o c 20 40 60 80 1. 5 2 .0 2.5 3.0 3.5 4. 0 0 i d, drain cur rent (a) v gs , g a t e to source voltage (v) pul se dura tion = 80 s dut y cycle = 0 .5% max v dd = 15v t j = 175 o c t j = 2 5 o c t j = - 55 o c 20 40 60 80 01 234 5 0 i d , drain curre nt (a) v ds , drain t o sour ce voltage (v) v gs = 3 v v gs = 3.5v v gs = 5 v v gs = 1 0v pul se durat ion = 80 s duty cycle = 0.5% max t c = 2 5 o c v gs = 4 v 30 35 40 45 50 24 68 1 0 25 i d = 1 5a v gs , ga te to source voltage (v) i d = 39a r ds( on) , drain to source on resistance (m ? ) i d = 2 7a p ul se duration = 80 s duty cycle = 0.5% max t c = 2 5 o c 1.0 1.5 2.0 2.5 3.0 - 80 - 4 0 0 40 80 120 160 20 0 0.5 no rmal ized drain to source t j , junct ion temperature ( o c) on re sistance v gs = 1 0v , i d = 39a pul se duration = 80 s duty cycle = 0.5% max h uf76633p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 4
figure 11. no rmalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an 7260. figure 14. gate charge waveforms for constant gate current figure 15. switching time vs gate resistance fi gure 16. switching time vs gate resistance t ypical performance curves ( continued) 0. 6 0.8 1. 0 1.2 -80 -40 0 40 80 120 160 200 0.4 n ormal ized gate t j , j uncti on temperature ( o c) v gs = v ds , i d = 250 a t hreshold v oltage 1. 0 1.1 1. 2 -80 -40 0 40 80 120 160 20 0 0. 9 t j , j unct ion temperature ( o c) norm aliz ed drain to source breakdown voltage i d = 2 50 a 10 0 1000 0 .1 1 10 10 0 50 00 10 c, capa citance (pf) v ds , drai n to source voltage (v) v gs = 0 v, f = 1mhz c i ss = c gs + c gd c o ss ? c ds + c gd c rss = c gd 2 4 6 8 10 0 102 0 3040506 0 0 v gs , g at e to source voltage (v) v dd = 50v q g , ga te charge (nc) i d = 3 9a i d = 2 7a wav eforms in descending order: i d = 1 5a 100 200 300 400 0 10 2030405 0 0 s wit ching time (ns) r gs , gat e to source resistance ( ? ) v gs = 4.5v, v dd = 5 0v, i d = 27a t r t f t d( on ) t d( off) 100 200 300 400 500 0 102 03 0405 0 0 swit ching ti me (ns) r gs , gat e to source resistance ( ? ) v gs = 1 0v , v dd = 5 0v , i d = 3 9a t d( off) t r t d( on ) t f h u f7 66 33p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 5
t est circuits and waveforms fi gure 17 . unclamped energy test circuit figure 18. unclamped energy waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms figure 21. switching time test circuit figure 22. switching time waveform t p v gs 0. 01 ? l i as + - v ds v dd r g dut va ry t p t o o btain required peak i as 0v v dd v ds bv ds s t p i as t av 0 r l v gs + - v ds v dd dut i g( ref) v dd q g( th) v gs = 1 v q g( 5) v gs = 5 v q g( to t) v gs = 1 0 v v ds v gs i g( ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d( on ) t r 90% 10 % v ds 90 % 10% t f t d( off) t of f 90 % 50% 50 % 10% pulse width v gs 0 0 h uf7 6633p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 6
p spice electrical model .su bc kt huf76633 2 1 3 ; rev 10 september1999 ca 12 8 3.50e-9 cb 15 14 3.50e-9 cin 6 8 1.70e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 120.7 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.00e-9 lgate 1 9 5.17e-9 lsource 3 7 2.13e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 2.04e-2 rgate 9 20 2.15 rldrain 2 5 10 rlgate 1 9 51.7 rlsource 3 7 21.3 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rso urcemod 4.85e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51) /abs(v (5,5 1)))*(pwr(v (5,5 1)/(1e -6*79) ,3.5))} .model dbodymod d (is = 1.96e-12 rs = 3.87e-3 trs1 = 9.93e-4 trs2 = 4.97e-6 cjo = 1.53e-9 tt = 7.41e-8 m = 0.50) .model dbreakmod d (rs = 3.12e- 1trs1 = 1.07e- 3trs2 = 0) .model dplcapmod d (cjo = 1.97e- 9is = 1e-3 0 m = 0.87) .model mmedmod nmos (vto = 1.73 kp = 2.80 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 2.15) .model mstromod nmos (vto = 2.04 kp = 80 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.50 kp = 0.10 is = 1e- 30 n = 10 tox = 1 l = 1u w = 1u rg = 21.5 rs = 0.1) .model rbreakmod res (tc1 = 9.74e- 4tc2 = -3.71e-7) .model rdrainmod res (tc1 = 9.71e-3 tc2 = 2.90e-5) .model rslcmod res (tc1 = 2.17e-3 tc2 = 1.27e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 0) .model rvthresmod res (tc1 = -2.08e-3 tc2 = -6.82e-6) .model rvtempmod res (tc1 = -1.52e- 3tc2 = -1.21e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -6.00 voff= -1.50) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -1.50 voff= -6.00) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.50 voff= 0.0) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.0 voff= -0.50) .ends n ot e: for further discussion of the pspice m odel, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1 991, written by william j. hepp and c. frank w heatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rv te mp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mw eak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rsl c2 1 ga te rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 h uf7 6633p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 7
s aber electrical model re v 10 s eptember 1999 template huf76633 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 1.96e-12, cjo = 1.53e-9, tt = 7.41e-8, m = 0.50) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.97e-9, is = 1e-30, m = 0.87 ) m..model mmedmod = (type=_n, vto = 1.73, kp = 2.8, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.04, kp = 80, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.50, kp = 0.1, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.00, voff = -1.50) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.50, voff = -6.00) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.50, voff = 0.0) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.0, voff = -0.50) c.ca n12 n8 = 3.50e-9 c.cb n15 n14 = 3.50e-9 c.cin n6 n8 = 1.70e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.17e-9 l.lsource n3 n7 = 2.13e-9 m.mmed n16 n6 n8 n8 = model=mmed mod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mst rongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.74e-4, tc2 = -3.71e-7 res.rdbody n71 n5 = 3.87e-3, tc1 = 9.93e-4, tc2 = 4.97e-6 res.rdbreak n72 n5 = 3.12e-1, tc1 = 1.07e-3, tc2 = 0 res.rdrain n50 n16 = 20.40e-3, tc1 = 9.71e-3, tc2 = 2.90e-5 res.rgate n9 n20 = 2.15 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51.7 res.rlsource n3 n7 = 21.3 res.rslc1 n5 n51 = 1e-6, tc1 = 2. 17e-3, tc2 = 1.27e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 4.85e-3, tc1 = 1.00e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.52e-3, tc2 = 1.21e-7 res.rvthres n22 n8 = 1, tc1 = -2.08e-3, tc2 = -6.82e-6 spe.ebreak n11 n7 n17 n18 = 120.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s 1amod sw_vcsp.s1b n 13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n 13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/79))** 3.5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rv te mp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mw ea k ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rsl c2 1 ga te rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbod y rdbreak 72 71 h u f7 66 33p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 8
s pice thermal model rev 9 sept ember1999 huf76633t ctherm1 th 6 2.90e-3 ctherm2 6 5 1.25e-2 ctherm3 5 4 1.00e-2 ctherm4 4 3 6.50e-3 ctherm5 3 2 2.75e-2 ctherm6 2 tl 12.55 rtherm1 th 6 7.04e-3 rtherm2 6 5 1.75e-2 rtherm3 5 4 4.94e-2 rtherm4 4 3 2.77e-1 rtherm5 3 2 4.18e-1 rtherm6 2 tl 5.54e-2 s aber thermal model sa ber t hermal model huf76633t template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.90e-3 ctherm.ctherm2 6 5 = 1.25e-2 ctherm.ctherm3 5 4 = 1.00e-2 ctherm.ctherm4 4 3 = 6.50e-3 ctherm.ctherm5 3 2 = 2.75e-2 ctherm.ctherm6 2 tl = 12.55 rtherm.rtherm1 th 6 = 7.04e-3 rtherm.rtherm2 6 5 = 1.75e-2 rtherm.rtherm3 5 4 = 4.94e-2 rtherm.rtherm4 4 3 = 2.77e-1 rtherm.rtherm5 3 2 = 4.18e-1 rtherm.rtherm6 2 tl = 5.54e-2 } r therm 4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th j unction cas e h uf7 6633p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 9
tr adema rks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. dis claimer fairchild semic onductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditio ns, specifically the warranty therein, which covers these products. li fe support po licy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product stat us definitions definition of terms 2cool? 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trifaul t detect? truecurrent ? * ser des? uhc ? ultra fr fet? unifet? vcx ? visualmax? voltageplus? xs? ? ? tm dat asheet identifi cation product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the ri ght to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fair child semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fai rchild se miconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . co unterf eiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts ex perience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing de lays. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages cu stomers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our custom ers to do their part in stopping this practice by buying direct or from authorized distributors. r ev. i61 tm ? h u f7 66 33p3 _f085 huf76633p3_f085 rev. c1 www.fairchildsemi.com 10
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